Senior DFT Engineer
Berkshire, Northamptonshire, England
Permanent
Excellent salary + pre-IPO shares
V-200531
Lucy Edmondson
ASIC | Verification | DFT
Senior DFT Engineer
Location: Switzerland (Lausanne), Germany (Dortmund), or UK (Northampton or Reading)
Are you an experienced DFT Engineer eager to drive innovation in the semiconductor industry? We have an exciting opportunity for a Senior DFT Engineer to join a high-tech, fast-growing company making strides in high-speed, energy-efficient chip-chip link solutions. If you’re passionate about pushing your limits and thrive in a challenging, forward-thinking environment, this could be the role for you.
Role overview:
As a Senior DFT Engineer, you will collaborate with multi-site teams to drive the design, implementation, and simulation of complex DFT architectures, managing projects from initial stages through to successful tape-outs. This role involves developing and leading DFT methodologies and tool flows for intricate, multi-million gate designs, including those with Analog/high bandwidth SerDes. You will define comprehensive test plans, contribute to functional and structural test development, and support the definition of HTOL test suites, cycle times, and burn-in PCB board bring-up.
Key Skills:
Please contact Lucy Edmondson at IC Resources for more information.
Apply now
Location: Switzerland (Lausanne), Germany (Dortmund), or UK (Northampton or Reading)
Are you an experienced DFT Engineer eager to drive innovation in the semiconductor industry? We have an exciting opportunity for a Senior DFT Engineer to join a high-tech, fast-growing company making strides in high-speed, energy-efficient chip-chip link solutions. If you’re passionate about pushing your limits and thrive in a challenging, forward-thinking environment, this could be the role for you.
Role overview:
As a Senior DFT Engineer, you will collaborate with multi-site teams to drive the design, implementation, and simulation of complex DFT architectures, managing projects from initial stages through to successful tape-outs. This role involves developing and leading DFT methodologies and tool flows for intricate, multi-million gate designs, including those with Analog/high bandwidth SerDes. You will define comprehensive test plans, contribute to functional and structural test development, and support the definition of HTOL test suites, cycle times, and burn-in PCB board bring-up.
Key Skills:
- Experience in DFT, including architecture specification, implementation, test pattern development, and verification.
- Proven expertise in MBIST insertion, simulation, and verification on RTL and Gate Level Netlist.
- Solid experience with Scan insertion, Scan compression, Stuck-At, At-Speed testing, and coverage analysis.
- Proficiency in Scan ATPG pattern generation, simulation, and debug on RTL and Gate Level Netlist.
- Hands-on experience with state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys).
- Familiarity with STA DFT test mode timing constraint development and analysis.
- Strong Verilog HDL knowledge, with experience in simulators and waveform debugging tools.
- Proficiency in TCL scripting; Python scripting skills are advantageous.
Please contact Lucy Edmondson at IC Resources for more information.
