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Senior Digital Verification Engineer

Hamburg, Germany,
Hanover, Lower Saxony


Depending on experience


World leader in SOC design and verification seeks UVM verification expert for IP verification duties, to join their team in Hannover which is known for the development and design of ASICs, SoCs, FPGAs, Embedded Software, and discrete Systems.  

Your qualifications and experience:
  • Bachelor or master's degree in electrical engineering
  • 5+ years of experience in the area of "Advanced Verification", proficient in SystemVerilog and UVM.
  • Knowledge of "Formal & Assertion Based Verification".
  • SystemC and C ++ a
  • Experience in dealing with the well-known simulation environments from Cadence, Mentor Graphics and Synopsys.
If you would like to know more, please contact Ane Bauer
Apply now