Free cookie consent management tool by TermsFeed Privacy Suite Generator Vacancy - Senior Digital Verification Engineer (ASIC / UVM) | Technology Recruitment

Senior Digital Verification Engineer (ASIC / UVM)

Lombardy, Milan, Italy


€40-70k (dependent on experience)


Working for a global player in the semiconductor industry, my client is a US based company who are looking to grow their UVM digital IC verification engineering department.

Required skills:
  • I am looking to speak to engineers with 3-5+ years' industry experience
  • Degree in Electronics/microelectronics, or similar field
  • 3-5+ years' industry experience
  • Excellent knowledge of UVM verification, IP verification, system verilog
  • UVM environments - set up test benches etc
  • Knowledge of analog / mixed-signal environments is a bonus
  • Fluent English / Italian skills
If you would like to know more, please contact Rob Hudson today!
Apply now