Senior Formal Verification Engineer

An established semiconductor company is looking to grow a new Formal Verification Team in Lisbon. 

This is a fantastic opportunity for an experienced Formal Verification Engineer to work on leading AI SoC and data centre projects. 

Lisbon is a brilliant city for working professionals and families alike, who wish to enjoy great weather, culture and food in a multicultural city.  

The key skills needed for the Senior Formal Verification Engineer are:

• Formal Verification for complex ASIC projects
• Simulation based verification using UVM/System Verilog
• Prior experience with formal verification methods and techniques 
• Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc. 
• Proficiency in programming/scripting languages 
• Strong experience with hardware description languages (EG: Verilog or VHDL) 

If you are interested in finding out more, or applying for this role, please contact Lucy Edmondson at IC Resources.