Senior / Lead Digital IC Design Engineer (ASIC full flow)

Grenoble, Auvergne Rhône Alpes


€70-90k depending on experience


Working for a cutting edge Semiconductor company in Grenoble, we have a great new role available as Senior Digital Design Engineer.

As Senior Digital Design Engineer, you will be responsible for defining and developing the full, ASIC design flow. So applicants must have significant IP design & development experience from concept, architecture definition, RTL design, implementation, synthesis, STA (timing), DFT to tape-out/release.

Also offering a friendly and collaborative work environment, with a family feel!

Skills / requirements:
  • Degree / Masters / PHD in Electronics / Micro-electronics / Physics etc.
  • Circa 10+ years' digital design experience
  • Confident ability in RTL design (Verilog / VHDL, SystemVerilog) for ASIC / FPGA
  • Proven ability in tape-out, IP development and delivery processes
  • Knowledge of the full digital design flow, from RTL2GDS
  • Physical design / implementation / place & route (P&R) for back-end
  • DFT - APTG / MBIST etc
  • STA / Timing Closure / timing constraints
  • synthesis / power
  • Good knowledge of verification - system verilog and UVM processes
  • embedded software development / firmware
For more information, please get in touch with your CV.
Apply now