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Senior RTL Design Engineer (ASIC / FPGA / SOC)

Paris, Île-de-France


salary dependent on level of experience


I am looking for a senior digital design engineer to join a friendly digital design team based in the Paris region. Working for a privately owned semiconductor company, you will focus on the latest developments in the semiconductor industry for space and aerospace applications.

You will be responsible for designing digital circuits (IPs - Intellectual Properties) to be integrated in the digital part of SoC FPGAs.

  • IPs specifications and architecture definition.
  • Realization of test plans.
  • RTL coding / verification / code coverage : Design and debug RTL logic
  • ATPG analysis and pattern generation.
  • Writing of technical documents
  • University or Engineering School degree (Bac + 5 or Bac + 8).
  • At least 5 years of industry or relevant experience in ASIC or FPGA development (preferably 10 years+)
  • Knowledge of RTL languages: Verilog or VHDL.
  • Knowledge of scripting languages (Python, Perl, Bash, etc.)
  • Good communication skills in English and French.
  • Having a tape-out experience is a plus.
For more information, please contact Rob Hudson 
Apply now