Senior UVM Verification Engineer
Grenoble, Auvergne Rhône Alpes
Permanent
Salary dependent on technical knowledge and years of experience
V-200313
Lucy Edmondson
ASIC | Verification | DFT
Job Opportunity: Verification Engineer
Grenoble
Are you a skilled Verification Engineer looking for a dynamic role in a fast-growing company where your contributions will be valued and visible? Do you thrive in a collaborative, innovative, and technical environment? If so, this could be the perfect opportunity for you!
A rapidly growing company, based in the Grenoble metropolitan area, is seeking multiple Verification Engineers to join their team. As a Verification Engineer, you will be at the forefront of cutting-edge projects, collaborating with a highly skilled team to design and verify complex systems for industries ranging from automotive and AI to energy and aerospace.
Key Responsibilities
As a Verification Engineer, you will:
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Grenoble
Are you a skilled Verification Engineer looking for a dynamic role in a fast-growing company where your contributions will be valued and visible? Do you thrive in a collaborative, innovative, and technical environment? If so, this could be the perfect opportunity for you!
A rapidly growing company, based in the Grenoble metropolitan area, is seeking multiple Verification Engineers to join their team. As a Verification Engineer, you will be at the forefront of cutting-edge projects, collaborating with a highly skilled team to design and verify complex systems for industries ranging from automotive and AI to energy and aerospace.
Key Responsibilities
As a Verification Engineer, you will:
- Define and implement verification methodologies tailored to complex projects.
- Lead the verification of advanced IPs and System-On-Chips, including the development of testbenches and verification plans.
- Leverage your expertise in SystemVerilog, UVM, and PCIe to ensure high-quality, functional verification.
- Mentor junior engineers, guiding their development and fostering a collaborative environment.
- Contribute to process improvements and explore innovative verification methodologies, including formal verification and PSS.
- Proven experience in verification, with a deep understanding of SystemVerilog, UVM, and PCIe.
- Proficiency in developing verification environments and writing detailed verification plans.
- Experience with RTL design languages like VHDL/Verilog is a plus.
- Strong problem-solving skills and a passion for continuous learning.
- Ability to work both independently and as part of a team.
- A proactive attitude, with the ability to think outside the box and provide creative technical solutions.
- Embedded software development (C/C++)
- Knowledge of FPGA and ASIC design
- Scripting languages like Python
- Familiarity with formal verification techniques