
SoC - ASIC Design Manager
Switzerland, Europe
Permanent
30-150k CHF plus package ( dependent on experience) - will consider higher for exceptionally qualified managers/engineers/applicants
V-219356

Rob Hudson
ASIC | Design | Architecture | Management UK/EU
Brand new role for a well-established player in the Semiconductor industry - based full-time in Switzerland.
Salary is negotiable - (based on seniority and relevance of experience) - circa 100-150k CHF plus package
I am looking for a SOC Design Manager; to be responsible for the end to end design, set-up, micro-architecture definition, definition of the whole process & desgin flow and RTL design of a digital - analog - mixed signal / AMS chip development and delivery projects.
As SOC Design Manager, your duties will include team leadership / management of a multi-functional and skilled team in charge of delivering the full chip to delivery at the fab.
Must have experience:
MUST HAVE - EU working rights.
Apply now
Salary is negotiable - (based on seniority and relevance of experience) - circa 100-150k CHF plus package
I am looking for a SOC Design Manager; to be responsible for the end to end design, set-up, micro-architecture definition, definition of the whole process & desgin flow and RTL design of a digital - analog - mixed signal / AMS chip development and delivery projects.
As SOC Design Manager, your duties will include team leadership / management of a multi-functional and skilled team in charge of delivering the full chip to delivery at the fab.
Must have experience:
- Degree / Masters / PhD in electronics / micro-electronics, physics or similar field
- 10-15+ years' experience of full chip design and delivery
- Tech lead / team leadership / team management
- Digital / AMS, analog-mixed-signal IP, chips and SOCs
- ASIC & FPGA - verilog, system verilog, VHDL
- ADC / DAC - digital - analog interfaces
- Functional verification - system verilog - IP, system, sub-system, block, top level experience
- Creation of test-benches
- detailed knowledge of complex tape-out processes, and interactions with fabrication plants
- Full digital design flow, from RTL2GDS
- SOC design, integration, system design, system architecture
- power management / PMIC / ultra-low power / optimisation & performance
- synthesis / HLS / STA
- physical implementation / physical design
- Understanding of software / firmware / embedded requirements
- PLLs / filter design
- RF-SOC
- DSP, signal processing
- Flash memory - DDR / HBM / high-bandwith memory / cache chorency
- clock, timing constraints
MUST HAVE - EU working rights.

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