SPE Verification Engineer
Atlanta, Georgia,
Georgia, Europe
Permanent
$129,200 - $239,900, based on skills, experience, and location.
V-211970
Meg Evans
ASIC | Verification
Senior Principal Verification Engineer
I am looking for a Senior Principal Verification Engineer to join a global leader in chip and Silicon IP innovation, where you'll help develop cutting-edge products that drive data performance and security.
Location: Johns Creek, GA, USA
Role Type: Full-Time
Work Environment: Hybrid (average of 3 days onsite, 2 days remote)
This role is within the Memory Interface Chip team, reporting to the Senior Director of Analog Engineering. As a Senior Principal Verification Engineer, you will play a critical role in the verification process, from creating detailed verification plans to implementing advanced methodologies. You will also mentor junior designers and collaborate with cross-functional teams to ensure robust product performance.
Key Responsibilities
Employees benefit from:
How to Apply For a confidential discussion regarding this role, please contact Meg Evans at IC Resources.
Apply now
I am looking for a Senior Principal Verification Engineer to join a global leader in chip and Silicon IP innovation, where you'll help develop cutting-edge products that drive data performance and security.
Location: Johns Creek, GA, USA
Role Type: Full-Time
Work Environment: Hybrid (average of 3 days onsite, 2 days remote)
This role is within the Memory Interface Chip team, reporting to the Senior Director of Analog Engineering. As a Senior Principal Verification Engineer, you will play a critical role in the verification process, from creating detailed verification plans to implementing advanced methodologies. You will also mentor junior designers and collaborate with cross-functional teams to ensure robust product performance.
Key Responsibilities
- Write SystemVerilog Assertions (SVA) to validate digital DUT behavior.
- Design and implement SystemVerilog test-benches and apply UVM methodologies for constrained random testing.
- Write SystemVerilog Assertions (SVA) to validate digital DUT behavior.
- Track and resolve bugs, functional coverage, and RTL code coverage metrics.
- Provide technical mentorship to junior members
- Proficiency in SystemVerilog and UVM methodology.
- DDR memory interface verification experience is highly desirable.
- Experience with Analog/Mixed-Signal products.
- Proven ability to lead and drive technical solutions within an organisation.
Employees benefit from:
- Competitive compensation, including salary, bonus, and equity options.
How to Apply For a confidential discussion regarding this role, please contact Meg Evans at IC Resources.
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