{"id":142699,"date":"2026-06-02T00:00:00","date_gmt":"2026-06-01T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/staff-asic-design-engineer-466371\/"},"modified":"2026-07-24T18:06:27","modified_gmt":"2026-07-24T17:06:27","slug":"staff-asic-design-engineer-466371","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/staff-asic-design-engineer-466371\/","title":{"rendered":"Staff ASIC Design Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">Due to growth, this is a fantastic opportunity to join a global company in their Cambridge office. The role<strong> <\/strong>offers broad ownership across the entire ASIC development cycle, from architecture and RTL design through verification, DFT, implementation, and silicon validation. <strong>The role combines challenging mixed-signal design work with the opportunity to provide technical leadership and contribute to design methodology improvements in one of the UK\u2019s leading technology and Semiconductor hubs.<\/strong><\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Key responsibilities<\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Design and develop functional digital blocks and contribute to the delivery of complete mixed-signal ASICs from concept through to full production maturity<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Support product definition activities through feasibility studies, architecture development, and FPGA-based digital emulation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Develop RTL designs in SystemVerilog that meet system performance, functionality, and quality requirements<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Create comprehensive block-level verification environments and testbenches to validate digital functionality<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Perform digital synthesis and develop appropriate physical design constraints to achieve power, performance, and area (PPA) targets<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Generate and maintain high-quality design documentation and actively participate in design reviews<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Provide technical leadership and mentorship to other team members<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Drive continuous improvement of digital design methodologies and best practices<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Skills and expertise<\/strong><\/span><\/p>\n<ul type=\"disc\">\n<li><span style=\"font-family: Verdana;font-size: 14px\">Have a minimum of 5 years&#8217; experience in digital IC design using standard-cell methodologies<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Possess deep knowledge of industry-standard digital design methodologies and best practices<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Demonstrate expertise in fully synthesised digital design flows, including RTL development and logic synthesis<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Be highly proficient in SystemVerilog and modern digital EDA toolchains<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Have experience applying timing and physical design constraints within automted place-and-route flows<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Understand production test requirements and have hands-on experience implementing DFT techniques such as scan-based testing to maximise test coverage<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Have practical experience with low-power digital design techniques and power optimisation methodologies<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Be proficient in scripting languages such as TCL and Python<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Benefits<\/strong><\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">A competitive compensation and benefits package is offered, including joining stock + Employee stock purchase scheme and a base salary.<\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Please contact Rachel Mason for more information.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Due to growth, this is a fantastic opportunity to join a global company in their Cambridge office. The role offers broad ownership across the entire ASIC development cycle, from architecture and RTL design through verification, DFT, implementation, and silicon validation. The role combines challenging mixed-signal design work with the opportunity to provide technical leadership and [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[408],"industry":[],"class_list":["post-142699","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Staff ASIC Design Engineer - England<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/en\/jobs\/staff-asic-design-engineer-466371\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Staff ASIC Design Engineer - England\" \/>\n<meta property=\"og:description\" content=\"Apply to Staff ASIC Design Engineer - Cambridgeshire, England. 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