{"id":180900,"date":"2026-07-17T00:00:00","date_gmt":"2026-07-16T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/dft-engineer-489101\/"},"modified":"2026-08-15T22:06:35","modified_gmt":"2026-08-15T21:06:35","slug":"dft-engineer-489101","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/dft-engineer-489101\/","title":{"rendered":"DFT Engineer"},"content":{"rendered":"

Help Build the Next Generation of AI Silicon<\/span><\/h3>\n

I’m currently working with an exciting, well-funded semiconductor company developing next-generation AI hardware designed to overcome one of the biggest challenges facing modern computing.<\/span><\/p>\n

As AI workloads continue to increase in complexity, the demand for faster, more efficient silicon has never been greater. This team is developing a cutting-edge AI accelerator architecture that will help redefine the future of high-performance computing.<\/span><\/p>\n

They’re now looking for a DFT Engineer<\/strong> to join the team implementing Design-for-Test for a large, multi-core AI accelerator ASIC.<\/span><\/p>\n

You’ll play a key role in delivering a scalable, production-ready DFT solution, working across scan implementation, ATPG, memory test and silicon bring-up. This is an excellent opportunity to develop your expertise while working alongside experienced engineers across architecture, RTL, physical design and product engineering.<\/span><\/p>\n

Responsibilities<\/span><\/h3>\n
    \n
  • Contribute to the DFT architecture of a complex multi-core AI accelerator SoC<\/span><\/li>\n
  • Integrate DFT methodologies and tools into the overall ASIC design flow<\/span><\/li>\n
  • Implement scan insertion, scan compression and associated test logic<\/span><\/li>\n
  • Generate, analyse and debug ATPG patterns for structural fault coverage<\/span><\/li>\n
  • Support MBIST implementation for large embedded memory arrays<\/span><\/li>\n
  • Work closely with Physical Design teams to ensure robust scan chain implementation and timing closure<\/span><\/li>\n
  • Develop scripting and automation to improve DFT efficiency and workflows<\/span><\/li>\n
  • Support silicon bring-up, manufacturing test and post-silicon debug<\/span><\/li>\n
  • Collaborate with Product and Test Engineering teams to support ATE bring-up, production test and yield improvement<\/span><\/li>\n<\/ul>\n

    What they’re looking for<\/span><\/h2>\n
      \n
    • Degree in Electronic Engineering, Computer Engineering or a related discipline<\/span><\/li>\n
    • Experience in DFT, digital IC design or ASIC development<\/span><\/li>\n
    • Good understanding of:<\/span>\n
        \n
      • Scan architecture<\/span><\/li>\n
      • ATPG<\/span><\/li>\n
      • MBIST<\/span><\/li>\n
      • Digital test methodologies<\/span><\/li>\n<\/ul>\n<\/li>\n
      • Familiarity with industry-standard EDA tools<\/span><\/li>\n
      • Scripting experience using Python, Tcl or similar languages<\/span><\/li>\n<\/ul>\n

        You’ll enjoy solving technical challenges, working collaboratively across engineering disciplines and developing your expertise on complex, leading-edge silicon.<\/span><\/p>\n

        You’re naturally detail-oriented, enjoy working on large-scale ASICs and are keen to grow your knowledge of Design-for-Test within a high-performing engineering team.<\/span><\/p>\n

        Why Join?<\/span><\/h2>\n
          \n
        • Work on genuinely innovative AI silicon with real-world impact<\/span><\/li>\n
        • Be part of a highly collaborative engineering culture<\/span><\/li>\n
        • Gain exposure across the full ASIC development lifecycle, from architecture through to silicon bring-up<\/span><\/li>\n
        • Work alongside experienced experts across hardware, software and systems engineering<\/span><\/li>\n
        • Take ownership of meaningful technical challenges while continuing to develop your career<\/span><\/li>\n<\/ul>\n

          If you’d like to hear more, I’d be happy to share further details in confidence. For more information, contact Rachel at IC Resources<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

          Help Build the Next Generation of AI Silicon I’m currently working with an exciting, well-funded semiconductor company developing next-generation AI hardware designed to overcome one of the biggest challenges facing modern computing. As AI workloads continue to increase in complexity, the demand for faster, more efficient silicon has never been greater. This team is developing […]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[718],"consultants":[408],"industry":[],"class_list":["post-180900","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"\nDFT Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to DFT Engineer - London, England. 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