{"id":210407,"date":"2026-09-02T00:00:00","date_gmt":"2026-09-01T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/lead-analog-layout-engineer-507189\/"},"modified":"2026-09-02T22:07:19","modified_gmt":"2026-09-02T21:07:19","slug":"lead-analog-layout-engineer-507189","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/lead-analog-layout-engineer-507189\/","title":{"rendered":"Lead Analog Layout Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">We are seeking a highly skilled and experienced Lead Analog IC Layout Engineer to join our dynamic team in Munich and to lead top-level chip planning and perform block-level custom layouts for CMOS and BiCMOS circuits in planar processes. You will be responsible for contractor based in Asia and India and must have previous experience guiding contractors. You will also play a key role in mentoring junior engineers and contribute to the development of standardized layout methodologies. This is an excellent opportunity for a seasoned professional with lead experience and a strong people skills to make a significant impact in a collaborative and innovative environment.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This role is fulltime on site in Munich and applications from across the EU will be considered if the applicant has a pre-existing work permit for Germany. (no visa sponsorship)<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">As a Lead Analog IC Layout Engineer, your key responsibilities will include:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Leading top-level chip planning and performing functional-block-level, block-level, sub-block-level, and leaf cell custom layouts for CMOS and BiCMOS circuits<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Conducting schematic-driven layouts and adhering to design constraints<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Designing die-area efficient layouts based on circuit designer requirements<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Performing floor-planning, power line planning, shielding, and device-matching layouts<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Verifying layouts and ensuring compliance with DRC, LVS, and ERC standards<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Contributing to chip-level routing, layout needs, integration, verification, and tape-out processes<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Collaborating with local and global design and layout teams across multiple time zones<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Training and mentoring junior layout engineers and offshore layout contractors<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Developing and implementing standard layout methodologies and workflows across sites<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Building processes and procedures to achieve high-quality layouts<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Supporting additional projects as assigned by management<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Qualifications and experience<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Industry degree in Microelectronics Engineering, BSc or higher<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">8+ years of experience in layout design for analog and full-custom digital blocks, IP Layout is not sufficient<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency in TSMC 65nm, 55nm, 28nm and 22nm process technologies<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Advanced skills in using layout editing tools within the Cadence Virtuoso design environment<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong knowledge of debugging DRC\/LVS\/ERC using Cadence PVS or Mentor Calibre<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Conceptual understanding of layout topics such as parasitics, matching, crosstalk, transistor layout-dependent effects, latch-up, IR drop, electro-migration (EM), and deep N-well and NTN isolation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proven ability to solve device matching, electro-migration, signal integrity, and power distribution challenges while adhering to area constraints<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience in chip-level floor planning, analog block integration, and tape-out processes<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Only candidates with an existing work permit for Germany will be consider. If you are interested in this opportunity, please contact Ane @ IC Resources with your CV and a time for an initial call.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are seeking a highly skilled and experienced Lead Analog IC Layout Engineer to join our dynamic team in Munich and to lead top-level chip planning and perform block-level custom layouts for CMOS and BiCMOS circuits in planar processes. You will be responsible for contractor based in Asia and India and must have previous experience [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[685],"consultants":[666],"industry":[],"class_list":["post-210407","jobs","type-jobs","status-publish","hentry","consultants-ane-bauer"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Lead Analog Layout Engineer - Germany<\/title>\n<meta name=\"description\" content=\"Apply to Lead Analog Layout Engineer - Bavaria, Germany. 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