{"id":214290,"date":"2026-08-20T00:00:00","date_gmt":"2026-08-19T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/principal-analog-ic-layout-engineer-503457\/"},"modified":"2026-09-11T02:06:11","modified_gmt":"2026-09-11T01:06:11","slug":"principal-analog-ic-layout-engineer-503457","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/principal-analog-ic-layout-engineer-503457\/","title":{"rendered":"Principal Analog IC Layout Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">We are seeking a highly skilled and experienced Principal Analog\/RF IC Layout Engineer to join our team. In this role, you will collaborate closely with the design team to layout and verify custom analog\/mixed-signal IPs. You will lead full-custom IC layout design and verification processes, including chip floor planning, analog IP layout, and chip-level layout integration of various analog, mixed-signal, and ASIC blocks. This is an excellent opportunity for a seasoned professional to contribute to cutting-edge technology in a dynamic and growing team. This position is office based.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Responsibilities<\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Lead the full-custom IC layout design and verification process, including chip floor planning and analog IP layout<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Perform chip-level layout integration of various analog, mixed-signal, and ASIC blocks<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Conduct full verification of block-level and top-level layouts, including extraction, DRC, LVS, and DFM checking<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Plan layout schedules and collaborate with other IP layout engineers to integrate various layout blocks<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Work closely with designers on block-level and top-level floor planning<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Review layouts for power\/gnd routing, electromigration, signal path checks, matching, and signal coupling<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Qualifications<\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Bachelor\u2019s degree in Engineering or a related field plus around 8-10 years of AMS IC Layout experience with expertise in high-speed and a strong understanding of parasitics in any process nodes, FinFets are not required but a nice to have<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency in Cadence Virtuoso design flow<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">High-level proficiency in interpreting CALIBRE DRC, ERC, and LVS reports<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Comprehensive understanding of IR drop, RC delay, electromigration, and chip finishing<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proven ability to perform floor planning and area estimation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong communication skills to effectively collaborate with circuit designers and other layout engineers<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with high-speed BiCMOS layout is a plus<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">If you are a dedicated professional with a passion for innovation and a proven track record in custom IC layout design, we encourage you to apply for this exciting opportunity. <\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Please contact Ane @ IC Resources with your CV and a time for an initial call!<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are seeking a highly skilled and experienced Principal Analog\/RF IC Layout Engineer to join our team. In this role, you will collaborate closely with the design team to layout and verify custom analog\/mixed-signal IPs. You will lead full-custom IC layout design and verification processes, including chip floor planning, analog IP layout, and chip-level layout [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[685],"consultants":[666],"industry":[],"class_list":["post-214290","jobs","type-jobs","status-publish","hentry","consultants-ane-bauer"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Principal Analog IC Layout Engineer - Switzerland<\/title>\n<meta name=\"description\" content=\"Apply to Principal Analog IC Layout Engineer - Zurich, Switzerland. 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