An ambitious semiconductor business developing advanced silicon for next-generation AI computing is seeking a Principal Physical Implementation Engineer to provide technical leadership across its ASIC implementation activities.<\/p>\n
This is an opportunity for an experienced Physical Design Engineer to take ownership of implementation quality, influence silicon development decisions and work across a broad range of engineering disciplines. The role combines hands-on technical expertise with responsibility for overseeing external implementation resources and shaping future internal capabilities.<\/p>\n
As Principal Physical Implementation Engineer, you will be responsible for ensuring complex silicon designs are physically implementable, optimised and ready for tape-out. Working closely with internal design teams and external engineering partners, you will provide technical direction throughout the backend development process, from early implementation planning through to final silicon sign-off.<\/p>\n
Key areas of responsibility include:<\/p>\n
\u2022 Establishing the technical approach for physical implementation, ensuring design requirements and implementation expectations are clearly defined from the outset.<\/p>\n
\u2022 Evaluating backend design deliverables, identifying potential issues across timing, power, area and physical implementation, and driving improvements where required.<\/p>\n
\u2022 Providing technical leadership to outsourced implementation teams, reviewing their approach, challenging proposed solutions and maintaining confidence in implementation quality.<\/p>\n
\u2022 Collaborating with RTL, architecture, verification and DFT engineers to address design decisions that influence physical implementation and overall silicon performance.<\/p>\n
\u2022 Taking ownership of implementation readiness, including reviewing sign-off evidence and assessing outstanding technical risks ahead of tape-out.<\/p>\n
\u2022 Contributing to integration decisions involving multiple dies, high-speed interconnects, memory and PHY components, with consideration for package and system-level constraints.<\/p>\n
\u2022 Working with external technology partners to resolve implementation challenges and support successful silicon delivery.<\/p>\n
\u2022 Identifying opportunities to improve backend processes, develop reusable methodologies and strengthen implementation infrastructure.<\/p>\n
\u2022 Supporting the development of internal engineering expertise, with the opportunity to establish and lead a dedicated Physical Implementation team as the organisation grows.<\/p>\n
\u2022 A highly experienced ASIC Physical Design professional <\/p>\n
\u2022 Demonstrable involvement in taking complex digital silicon from implementation through to successful fabrication.<\/p>\n
\u2022 Strong practical knowledge of backend design optimisation, including PPA, timing convergence, clock distribution and physical sign-off.<\/p>\n
\u2022 Confidence working with timing constraints, implementation requirements and methodologies across sophisticated ASIC designs.<\/p>\n
\u2022 Familiarity with leading industry EDA environments and the ability to independently assess implementation results and tool outputs.<\/p>\n
\u2022 Experience navigating integration challenges involving embedded memories, third-party IP and high-speed interface components.<\/p>\n
\u2022 Knowledge of low-power design implementation and associated power intent requirements.<\/p>\n
\u2022 The ability to operate as a technical authority, providing direction to external engineering teams and making informed implementation decisions.<\/p>\n
\u2022 Strong problem-solving capabilities and the confidence to operate within a developing silicon organisation where technical ownership is important.<\/p>\n
\u2022 Involvement in chiplet-based silicon or multi-die integration projects.<\/p>\n
\u2022 Understanding of advanced packaging considerations and their influence on backend design decisions.<\/p>\n
\u2022 Previous involvement in establishing or refining physical design flows and implementation standards.<\/p>\n
\u2022 Exposure to collaboration with semiconductor foundries, EDA providers and external IP or memory vendors.<\/p>\n
\u2022 Experience coaching engineers or taking responsibility for developing technical teams.<\/p>\n
For more information on this role or others then please contact Jordan Browne at IC Resources for more information. <\/span><\/p>\n","protected":false},"excerpt":{"rendered":" An ambitious semiconductor business developing advanced silicon for next-generation AI computing is seeking a Principal Physical Implementation Engineer to provide technical leadership across its ASIC implementation activities. This is an opportunity for an experienced Physical Design Engineer to take ownership of implementation quality, influence silicon development decisions and work across a broad range of engineering […]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[718],"consultants":[239],"industry":[],"class_list":["post-241761","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"\n