{"id":241761,"date":"2026-10-07T00:00:00","date_gmt":"2026-10-06T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/sta-engineer-527198\/"},"modified":"2026-10-17T10:12:48","modified_gmt":"2026-10-17T09:12:48","slug":"sta-engineer-527198","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/sta-engineer-527198\/","title":{"rendered":"STA Engineer"},"content":{"rendered":"<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">An exciting opportunity has arisen for an STA Engineer to join an innovative semiconductor company developing next-generation ASIC technology.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working within a growing and highly technical engineering team, the STA Engineer will play an important role in preparing complex designs for physical implementation, with responsibility across timing, low power and implementation readiness. With the company continuing to grow, the role offers excellent opportunities for career progression and the potential to develop into a technical leadership position over time.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">The role will involve:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Developing and maintaining SDC timing constraints across internal designs and third-party IP<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting static timing analysis and timing closure<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working with UPF and low power methodologies across different design partitions<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Preparing synthesis and implementation collateral<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working closely with physical design teams and external implementation partners<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Contributing to floorplanning, partitioning and implementation planning<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting power analysis, DFT and wider implementation activities<\/span><\/li>\n<\/ul>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">The ideal candidate will have:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience in ASIC implementation, STA or a closely related discipline<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Strong knowledge of SDC and static timing analysis<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience with synthesis and front-end implementation flows<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Practical understanding of UPF and low power design<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience working with SRAMs, memory macros and third-party IP<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Good understanding of physical design and floorplanning<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Previous tapeout experience would be advantageous<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience working in a Linux environment<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">All&nbsp;candidates&nbsp;must&nbsp;have&nbsp;the&nbsp;right&nbsp;to&nbsp;work&nbsp;in&nbsp;the&nbsp;Netherlands<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">For more information on this role or others then please contact Jordan Browne at IC Resources for more information.&nbsp;<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>An exciting opportunity has arisen for an STA Engineer to join an innovative semiconductor company developing next-generation ASIC technology. Working within a growing and highly technical engineering team, the STA Engineer will play an important role in preparing complex designs for physical implementation, with responsibility across timing, low power and implementation readiness. With the company [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[718],"consultants":[239],"industry":[],"class_list":["post-241761","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.6 (Yoast SEO v28.6) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>STA Engineer - Netherlands<\/title>\n<meta name=\"description\" content=\"Apply to STA Engineer - North Brabant, Netherlands. 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