{"id":241762,"date":"2026-10-07T00:00:00","date_gmt":"2026-10-06T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-staff-tools-methodology-engineer-527197\/"},"modified":"2026-10-17T10:12:48","modified_gmt":"2026-10-17T09:12:48","slug":"senior-staff-tools-methodology-engineer-527197","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/senior-staff-tools-methodology-engineer-527197\/","title":{"rendered":"Senior\/Staff Tools &amp; Methodology Engineer"},"content":{"rendered":"<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">An exciting opportunity has arisen for a Senior\/Staff Tool &amp; Methodology Engineer to help shape the development infrastructure and engineering methodologies behind a new generation of advanced silicon products.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working within a growing and highly technical engineering team, you will have a broad influence across the ASIC development flow, building the automation, EDA infrastructure and methodologies that enable engineers to develop, verify and deliver complex silicon efficiently. The role offers the opportunity to take ownership of key engineering infrastructure while helping define how the organisation approaches scalable silicon development.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">The role will involve:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Developing and maintaining EDA flows covering simulation, synthesis, lint, CDC, formal and power analysis<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Building automation and productivity tools using Python, Tcl and CI\/CD methodologies<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Improving development infrastructure, regression environments and engineering workflows<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting the deployment and management of EDA tools and design environments<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Helping introduce AI-assisted approaches across design, verification and implementation workflows<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Establishing flow quality standards, sign-off criteria and engineering metrics<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working closely with engineers to support methodology adoption and resolve flow-related challenges<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Driving continuous improvements to the way silicon projects are developed and delivered<\/span><\/li>\n<\/ul>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">The ideal candidate will have:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Strong commercial experience in ASIC methodology, EDA flows or a closely related area<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Excellent Python and Tcl scripting skills<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience working with leading EDA tools from vendors such as Synopsys, Cadence or Siemens EDA<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Good understanding of ASIC development flows including simulation, synthesis, lint and CDC<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Strong Linux development experience<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience supporting at least one production tapeout<\/span><\/li>\n<\/ul>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">All&nbsp;candidates&nbsp;must&nbsp;have&nbsp;the&nbsp;right&nbsp;to&nbsp;work&nbsp;in&nbsp;the&nbsp;Netherlands<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">For more information on this role or others then please contact Jordan Browne at IC Resources for more information.&nbsp;<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>An exciting opportunity has arisen for a Senior\/Staff Tool &amp; Methodology Engineer to help shape the development infrastructure and engineering methodologies behind a new generation of advanced silicon products. Working within a growing and highly technical engineering team, you will have a broad influence across the ASIC development flow, building the automation, EDA infrastructure and [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[688,718],"consultants":[239],"industry":[],"class_list":["post-241762","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.6 (Yoast SEO v28.6) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior\/Staff Tools &amp; Methodology Engineer - Netherlands<\/title>\n<meta name=\"description\" content=\"Apply to Senior\/Staff Tools &amp; Methodology Engineer - North Brabant, Netherlands. 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