{"id":241765,"date":"2026-10-08T00:00:00","date_gmt":"2026-10-07T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/digital-synthesis-engineer-527935\/"},"modified":"2026-10-17T10:12:50","modified_gmt":"2026-10-17T09:12:50","slug":"digital-synthesis-engineer-527935","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/digital-synthesis-engineer-527935\/","title":{"rendered":"Digital Synthesis Engineer"},"content":{"rendered":"<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">An exciting opportunity has arisen for a Digital Synthesis Engineer to join our client\u2019s engineering team and contribute to the development of advanced semiconductor products.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working within a highly technical engineering environment, you will play an important role in taking digital designs through synthesis and helping deliver robust, high quality implementations. The position offers exposure across the wider ASIC development flow, working closely with design, verification and physical implementation engineers to optimise designs for performance, power and area.<\/span><\/p>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">As a Digital Synthesis Engineer, you will be involved in:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Developing and running synthesis flows for complex digital designs and IP<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Preparing and managing synthesis constraints for block and top level designs<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Analysing timing, area and power results and identifying opportunities for optimisation<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working closely with RTL designers to resolve synthesis and implementation challenges<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting design integration and ensuring blocks are suitable for downstream implementation<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Investigating critical paths and helping improve overall design performance<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting physical design activities and resolving issues between front end and back end teams<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Contributing to improvements across synthesis methodologies, flows and development processes<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Working with engineers across the ASIC development lifecycle to support successful silicon delivery<\/span><\/li>\n<\/ul>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">The ideal candidate will have:<\/span><\/p>\n<ul>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience in digital ASIC, SoC or IC development<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Strong experience with synthesis and digital implementation flows<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Good understanding of RTL and Verilog\/SystemVerilog<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience working with timing constraints and analysing synthesis results<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Understanding of timing, power and area optimisation<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with ASIC development methodologies and the wider RTL to silicon flow<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Experience working in a Linux or Unix environment<\/span><\/li>\n<li class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">Good scripting or programming skills would be beneficial<\/span><\/li>\n<\/ul>\n<p class=\"isSelectedEnd\"><span style=\"font-family: Verdana;font-size: 14px\">For more information on this role or others then please contact Jordan Browne at IC Resources.&nbsp;<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>An exciting opportunity has arisen for a Digital Synthesis Engineer to join our client\u2019s engineering team and contribute to the development of advanced semiconductor products. Working within a highly technical engineering environment, you will play an important role in taking digital designs through synthesis and helping deliver robust, high quality implementations. The position offers exposure [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[718],"consultants":[239],"industry":[],"class_list":["post-241765","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.6 (Yoast SEO v28.6) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Digital Synthesis Engineer - Germany<\/title>\n<meta name=\"description\" content=\"Apply to Digital Synthesis Engineer - Baden Wurttemberg, Germany. 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