{"id":246541,"date":"2026-10-21T00:00:00","date_gmt":"2026-10-20T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-ic-layout-engineer-534522\/"},"modified":"2026-10-21T22:13:03","modified_gmt":"2026-10-21T21:13:03","slug":"senior-ic-layout-engineer-534522","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/senior-ic-layout-engineer-534522\/","title":{"rendered":"Senior IC Layout Engineer"},"content":{"rendered":"<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">This is a solid, stable opportunity for a Senior Analog IC Layout Engineer with a world-leading high-tech company based in Southampton. A flexible working set up is available with this role, with the ability to build up extra days off with flexi-working. &nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Please note, candidates for this role need to be eligible for security clearance. <\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Working within an expanding mixed-signal IC design team of 10+ engineers, the Senior Analog IC Layout Engineer will be working at transistor level to translate schematic designs into layout solutions. This team is a long-established group of IC design experts that bring deep expertise within a highly niche area, which is critical to several strategic sectors. <\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">The Senior IC Layout Engineer will have a number of years\u2019 experience in industry, a clear understanding of layout best practices and the ability to complete bespoke Analog\/Mixed Signal and Digital Layout designs in CMOS technology.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Experience is required in some or all of the following:&nbsp;<\/span><\/p>\n<ul style=\"margin-top: 0cm;margin-bottom: 0cm\" type=\"disc\">\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">DRC and LVS<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Top Level Verification<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Experience working on 40nm and below<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Cadence IC design suite of tools.<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Analog\/Mixed Signal and\/or Digital IC design skills\/knowledge<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Parasitic extraction and evaluation<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">Layout of block level designs from scratch, working on schematic capture and simulation of the designs<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">On offer is a competitive base salary, and a truly superb benefits package including a weighty pension scheme, private medical insurance and flexi-days, with the potential to take up to 45 days total annual leave in a year. <\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 10.0pt\">For more details or to apply, please contact Caroline Pye at IC Resources.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This is a solid, stable opportunity for a Senior Analog IC Layout Engineer with a world-leading high-tech company based in Southampton. A flexible working set up is available with this role, with the ability to build up extra days off with flexi-working. &nbsp; &nbsp; Please note, candidates for this role need to be eligible for [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709,680],"job_skillset":[685],"consultants":[344],"industry":[],"class_list":["post-246541","jobs","type-jobs","status-publish","hentry","consultants-caroline-pye"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.6 (Yoast SEO v28.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior IC Layout Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to Senior IC Layout Engineer - Hampshire, England. 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