{"id":90094,"date":"2026-03-24T00:00:00","date_gmt":"2026-03-24T00:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-staff-digital-asic-design-engineer-432732\/"},"modified":"2026-07-24T22:08:08","modified_gmt":"2026-07-24T21:08:08","slug":"senior-staff-digital-asic-design-engineer-432732","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/en\/jobs\/senior-staff-digital-asic-design-engineer-432732\/","title":{"rendered":"Senior\/Staff Digital ASIC Design Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">A leading Semiconductor company is looking for an experienced Senior \/ Staff Digital Design Engineer to lead digital design initiatives for advanced power management ICs. This role provides ownership of both existing IP and new designs, with close collaboration across multidisciplinary teams.<\/span><\/p>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Role overview<\/span><\/h3>\n<p><span style=\"font-family: Verdana;font-size: 14px\">As a Senior \/ Staff Digital Design Engineer, you will drive the digital core development from RTL to final GDS, ensuring high-quality, low-power designs. You will work with verification engineers to identify and resolve issues early, contribute to block-level architecture, and support the evolution of digital IP for current and upcoming platforms.<\/span><\/p>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Key responsibilities<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Lead digital core design for sophisticated power management solutions.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Develop new IP and optimise existing designs, defining effective block-level architectures.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Collaborate with verification teams to ensure functionality and performance before tape-out and for subsequent revisions.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Manage synthesis, timing closure, DFT, and coordinate physical implementation with external design partners.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Document design work and maintain clear internal technical specifications.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Apply low-power design techniques, including clock gating, while producing robust RTL code.<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Candidate profile<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Degree in Electrical \/ Electronic Engineering (MEng preferred) or equivalent<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong experience in SystemVerilog RTL design and verification across the full design and synthesis flow.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with synchronous and asynchronous design, and low-power techniques.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency with Cadence or equivalent design and simulation tools; scripting experience (Python, TCL, CSH) highly desirable.<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Compensation<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Base salary range: \u00a365,000\u2013\u00a375,000 per year, depending on experience.<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Additional benefits include performance bonuses, equity opportunities, and standard industry benefits.<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This is an excellent opportunity for a Senior \/ Staff Digital Design Engineer to influence next-generation digital ICs within a forward-thinking engineering environment. They also are offering VISA sponsorship for candidates outside of the UK as well.&nbsp;<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">For more information or to apply, please contact Jordan Browne at IC Resources. <\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>A leading Semiconductor company is looking for an experienced Senior \/ Staff Digital Design Engineer to lead digital design initiatives for advanced power management ICs. This role provides ownership of both existing IP and new designs, with close collaboration across multidisciplinary teams. Role overview As a Senior \/ Staff Digital Design Engineer, you will drive [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[408],"industry":[],"class_list":["post-90094","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior\/Staff Digital ASIC Design Engineer - England<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/en\/jobs\/senior-staff-digital-asic-design-engineer-432732\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Senior\/Staff Digital ASIC Design Engineer - England\" \/>\n<meta property=\"og:description\" content=\"Apply to Senior\/Staff Digital ASIC Design Engineer - Hertfordshire, England. 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