ASIC Design Contract, Lyon

IC Resources is currently working with an interesting client based in France who are looking for an ASIC design engineer to join the team for a project that is due to start early Feb. The client are looking for an engineer with particular low power experience who can create the RTL coding from scratch. There would also be some integration work for third party IP that the client has purchased so any experience with Synthesis and Timing would also be beneficial.

• 5+ years RTL design Experience
• Verilog/System Verilog Experience
• Low power design Experience
• Exposure to Matlab
• Onsite in Grenoble

Due to he requirement of an onsite ramp-up and occasional visits to site candidates must already hold relevant work VISA's for the EU