Fantastic opportunity for an ASIC Design Engineer to work in Paris with experience in Cache architecture and Interconnect technology!
This is a great time to join a growing business and have the opportunity to contribute to the backbone of the some of the world's most popular SoCs! You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You’ll have to ensure that IPs are matching the specifications before been released to your customers, to be part of a SoC for AI, IoT, automotive and mobile... their IP is used everywhere!
As part of this position you will have responsibilities which include writing micro architecture specification for highly configurable Ips as well as developing or upgrading Ips RTL description with performance, power and area goals. To be successful you must be able to work closely with Verification teams and
communicate well with wider members of the business. Experience Requirements / Qualifications:
- Must have at least 7 years of industry experience as a Design Engineer
- Knowledge of Verilog or SystemVerilog.
- Knowledge of interconnect technology is a plus
- Knowledge of Cache architecture is a plus.
- Knowledge of AMBA protocols.
For more information and a confidential discussion on this exciting opportunity please contact Rachel Mason at IC Resources.