ASIC Design Engineer
Oxfordshire, England
Permanent
Competitive salary
V-170404
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Rachel Mason
ASIC | Verification
ASIC Design Engineer! Superb Oxfordshire location! Excellent Salary and benefits!
This is a superb opportunity for an engineer ideally between 2-6 years of experience to join my client in Oxfordshire. Based in a City full of culture and beautiful scenery as well as having a good nightlife and plenty of activities this is a great location!
This role would suit both a junior engineer ready for the next step in their career or a mid-level to Senior looking to take on more responsibilities and be a key member within the organisation.
In this role, you will work closely with other ASIC team members, as well as with cross functional teams including design, architecture, firmware and validation. You will get a chance to utilize and develop your ASIC design and verification skills developing ASICs.
Essential skills for this role include an experience range from 2-6 years, experience translating design requirements into RTL, digital logic design and/or verification including implementation of multiple clock domains, conducting synthesis issues, design issues and timing violations as well as scripting language in Perl/Python/Tcl.
Desirable skills:
Apply now!! Or contact Rachel Mason for more information!
This is a superb opportunity for an engineer ideally between 2-6 years of experience to join my client in Oxfordshire. Based in a City full of culture and beautiful scenery as well as having a good nightlife and plenty of activities this is a great location!
This role would suit both a junior engineer ready for the next step in their career or a mid-level to Senior looking to take on more responsibilities and be a key member within the organisation.
In this role, you will work closely with other ASIC team members, as well as with cross functional teams including design, architecture, firmware and validation. You will get a chance to utilize and develop your ASIC design and verification skills developing ASICs.
Essential skills for this role include an experience range from 2-6 years, experience translating design requirements into RTL, digital logic design and/or verification including implementation of multiple clock domains, conducting synthesis issues, design issues and timing violations as well as scripting language in Perl/Python/Tcl.
Desirable skills:
- Understanding of formal verification techniques
- Experience with System Verilog and UVM test benches
- knowledge of writing system Verilog assertions
- Familiarity with C/C++
Apply now!! Or contact Rachel Mason for more information!