Whether you are a Junior ASIC Engineer, or Senior/Principal/Staff I have a fantastic opportunity in either Bristol or Cambridge and working with one of Europe’s hottest start-ups.
Their team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology.
As an RTL Engineer you will be responsible for defining and implementing microarchitecture for the IPU chips, working closely with the architecture, verification and physical design teams. The IPU chips have a wide variety of design challenges which you will need to have some working understanding of; these include processor design, application specific blocks, high-speed serial interfaces, complex third-party IP integration and design-for-test. Responsibilities
Requirements (some of)
- Microarchitecture documentation
- RTL implementation
- Providing feedback to architecture, verification and physical design teams
- Providing support for Verification debug and physical implementation
- Maintaining good communication across teams and sites
- System Verilog
- Ability to program, required to solve design issues, e.g. Python, Tcl
- Arithmetic pipeline
- Design for test
- Synthesis and Timing Analysis
- Logical Equivalence and Digital design flows
For more information and a confidential discussion please contact Rachel Mason at IC Resources – 0118 9881107