ASIC RTL Design Engineer – Farnborough
This is an interesting opportunity for an ASIC Design Engineer who will join my client’s team and will have responsibilities which include designing of next-generation satellite communication systems based on in-house developed chipsets.
As part of the role, you will be part of a dynamic and motivated silicon design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. Qualifications, Experience and Competencies
- Low Power, multi clock domain design experience.
- A wide and varied understanding of Digital Design Techniques and practices.
- Must have Digital Signal Processing (DSP) blocks RTL design experience.
- Ability to develop RTL in Verilog.
- RTL Synthesis with Cadence.
- Understanding of System VERILOG based Test benches.
- Scripting with either Perl, Shell, TCL, Python.
For more information and a confidential discussion please contact Rachel Mason at IC Resources.