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ASIC Design Engineer, Surrey


ASIC Design Engineer, Reading


Job ID: 174790
Location: Surrey, Hampshire, Buckinghamshire, Berkshire, England, UK
Salary: £40,000 - £55,000 depending on experience level
Job Type: Permanent


Digital ASIC design engineer – Thames Valley (Mid-level)

I am looking for an ASIC Design Engineer with a minimum of 3 years’ experience to join my client’s group in the Thames Valley region.

The successful engineer will be located in a modern town surrounded by some of England's finest countryside and famous attractions, enriched with Victorian parks, gardens and museums. This is a great location which has the best of both worlds, quiet but equally close to other major towns and cities!

Reporting to the Digital design Manger the successful digital design engineer will have ASIC design experience across all front-end stages of the digital design flow.

Required skills:
  • Minimum 3 years’ experience in ASIC/FPGA design.
  • Proficient in VHDL and/or Verilog for synthesizable RTL design and their synthesis.
  • Proficient in VHDL and/or Verilog for behavioural system simulations
  • Ability to write code and scripts in C, Python and Tcl.
  • Familiar with SoC architectures.
  • Ability to diagnose complex behaviours in hardware, software and simulation.
 Desirable skills:
  • Familiar with automotive standards
You will have the opportunity to be engaged in activities across the complete ASIC design spectrum, working in small cross-functional teams, thus gaining the skills for more senior roles.

For more information and a confidential discussion please contact Rachel Mason at IC Resources.


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