Senior and Principal Digital Design Engineers – NEW UK Design Centre in CAMBRIDGE! VC-backed start up with Stock options, fantastic company culture and huge growth! You will be required to relocate to Cambridge for this role and onsite working is expected
however my client have fantastic perks which include:
- 10 days working anywhere in the world remote (no holiday allowance will be taken)
- All employees are allowed to work in any of my clients’ global offices at any time (1 month, 2 months with family etc) including their HQ in Sydney!
After a couple of years of huge growth and branching out into Europe and the USA my Australian based start-up are expanding into the UK – They have recently moved to Cambridge.
My client are a team of wireless experts that love to innovate and invent! Together, they are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. The team include the original inventors of Wi-Fi and designers of Wi-Fi chips that have shipped inside many billions of devices.
For this role you will have a broad range of digital design and verification skills and strong industry experience in designing low-power mixed-signal SoCs.
I am looking for an expert digital design and verification engineers with 7+ years’ experience (12+ for Principal) developing mixed-signal chips. Your responsibilities will include Chip and block-level design and verification, enhancement of design and verification infrastructure and assisting with tapeout duties such as system verification, synthesis, gate level netlist simulations to validate design, power intent, and power analysis as well as using scala chisel compiler to do RTL coding.
I am keen to find someone who can make a real difference in a VC-backed startup and work in a dynamic & fun environment!
- Digital design and verification experience with 7+ years (12+ for Principal) relevant industry experience
- A deep understanding of digital design fundamentals including low power and multi-clock-domain design for mass-produced chips.
- Expert in ASIC design and simulation, experience with AMS simulation is a plus
- Very experienced with Cadence or Synopsys
- Experience defining functional verification requirements, implementing tests to meet them
- Expert in HDL languages such as Verilog, SystemVerilog or VHDL
- Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus
- A good understanding of embedded processor systems, familiarity with RISC-V is a plus
- Experience writing embedded C
- Hands-on experience with Linux development environment and scripting in Python.
As a company they have an excellent benefits package including stock option plan and competitive salary as well as relocation allowance, sponsorship for a European based engineer and great office perks!
For more information and a confidential discussion please contact Rachel Mason at IC Resources - APPLY NOW to be part of their next period of growth and cementing themselves here in the UK.