ASIC Timing and STA Engineer! Global Semiconductor Giant! Based in their European HQ!
This is a superb opportunity for a Timing STA Engineer to join my clients Global SoC team in their European HQ. You will be part of the design team that will drive and execute on all phases of the ASIC design flow for products at the core and chip-level using leading-edge CMOS process nodes with 10nm/7nm devices in production.
This is a truly fantastic time to join one of the biggest names in the Semiconductor world and working with advanced technologies. About the role
As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile and IOT markets. You will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level. You will also get the opportunity to facilitate and drive STA methodology. Preferred Qualifications
- Timing analysis, Timing Sign off and Timing Convergence execution experience
- Experience with all aspects of STA of SoC or Processor designs.
- Good understanding of library, derates, AOCV/POCV and intricate dependency on timing analysis
- Experience on programming in Perl, TCL, python.
- Experience in working with advanced process nodes (14 nm, 12 nm, 10 nm, 7 nm, 5nm)
- Familiar with circuit SPICE modeling
- Familiarity with timing and power ECO techniques
- Knowledge of digital/analog/mixed circuit design
- Ability to understand any STA tool (Synopsys/cadence/mentor graphics etc.)
- Knowledge of standard cell library development is a plus
As a top company my client offer superb benefits including RSU's, competitive salaries, health and life insurance + lots more! Relocation assistance is also provided.
For a confidential discussion and to find out more, Please contact Rachel Mason at IC-Resources