IC Resources is currently looking for a Digital Verification engineer who can join one of their clients based in the south west of the UK on a contract basis. Successful candidates must be able to join by the end of July and have a minimum of 7 years experience as they expect a significant amount of remote working to be on offer due to COVID restrictions. If you fulfill the below requirements and would like to discuss the role further, please get in touch to hear more.
Eligibility Criteria :
Minimum 7 years of experience as IP Digital Verification Engineer with System Verilog UVM (SoC/Subsystem is experience is NOT preferred).
Must be available for at least 1 year, preferably longer.
Must be very good in time management.
Must be a very good team player – able to work with engineers of different levels of experience.
A self-starter and a quick learner.
Excellent communication skills.
Familiarity with version management tools.
Nice to have tool specific experiences in :
Specman - Writing and debugging test-bench generation constraints
Incisive or Xcellium
Key Responsibilities of the Role :
Work as part of a team and implement parts of test bench using System Verilog UVM.
Develop System Verilog models for complex arithmetic or logic operations, scoreboards, monitors.
Efficiently debug SV model or c-model or RTL.
Analyzing test regression fails, debugging and fixing existing code as well.
Develop Efficient Coverage model and effectively close coverage targets.