ASIC Verification Engineer, Stuttgart

ASIC Verification Engineer, Stuttgart

Job ID: 170863
Location: Stuttgart, Baden-Wurttemberg, Germany, Europe
Salary: Excellent salary + benefits
Job Type: Permanent

For our client, a semiconductor leader in Stuttgart, Germany we are looking for an ASIC Verification Engineer.

For this technically challenging position as an ASIC Verification Engineer we are looking for digital verification engineers with an experience in digital verification of at least 3-5 years. As an ASIC Verification Engineer you will require solid knowledge of HW description languages like Verilog, SystemVerilog or similar, a university degree in Electrical Engineering or Electronics or equivalent and solid debugging skills and experience with UVM. For this position you also bring good C/C++ knowledge for verification.

In the position of an ASIC Verification Engineer you will:
  • Develop verification solutions for ASICs
  • Carry out functional verification planning and develop test cases
  • Constantly improve the script environment
  • Develop prototyping solutions
  • Initiate the introduction of new tools
If this vacancy as an ASIC Verification Engineer sounds appealing to you, please contact Nicole Lamprecht.

+44 (0)118 988 1150

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