My client is looking for an experienced Power Management Analog Design engineer who can apply their skills to highly integrated SoC with mixed signals in the cellular communication area. The daily work will include:
- Block level transistor design, simulation, layout and verifications with cadence environment
- Deliver circuits meeting tape out spec, quality and time schedule;
- Prepare signoff design and simulation report;
- Participate in design review work
Person Specification: Required:
- A proven background in SoC power management system and transistor level design.
- Excellent understanding of IC design process with CMOS technology.
- Excellent communication skill
- The candidate need to be familiar with Cadence
- Understanding of switching SIMO converters
- One or more design experience of the following circuits are required:
- DC-DC LDOs, oscillator/clock drivers, bandgap, comparators;
- Required knowledge of CMOS device physics, reliability, ESD
- Lower power design techniques
- Experience with cellular transceivers
- Familiar with CMOS design process geometries below 40nm;
- Familiar with mixed signal SoC design concepts and considerations;
- 5+ of analogue IC design
If interested in discussing this further, please get in touch with Mitchell Carpenter at IC Resources.