A high-tech start up in London is looking for an Analog IC Layout Engineer with a keen interest in cutting edge technology and striving to contribute their skills to the development of unique product and not shy to venture beyond established rules. You will be rewarded with an excellent company share package.
In your position as Analog IC Layout Engineer, you will be involved in the layout of Analog and Digital IP capable of operating at cryogenic temperatures as well the layout and characterisation of qubits based on commercial CMOS processes.
Your responsibilities are:
- Hands-on block-level layout design and verification
- Parasitic extraction and optimisation of layouts in close collaboration with the design team
- Top -level floor-planning, routing and signoff
- Provide tool/flow support for analogue and layout design teams
- Document own work and perform layout reviews with other team members
The successful Analog IC Layout Engineer has at least 3 years of experience in from within a similar position in the Semiconductor industry in a Cadence environment.
- Proficiency in Cadence Virtuoso Layout Suite (X)L including PCell Designer
- Experience with 40nm processes and below, including familiarity with layout-dependent effects (LOD, WPE, OSE, etc.)
- Proficiency in DRC, LVS, & Parasitic Extraction with Mentor Calibre or Cadence PVS/QRC
- Demonstrated experience in deep sub-micron processes
- Team player with a collaborative mind set
- Excellent verbal and written communication skills.
- Solid understanding of the Linux OS
- Experience in PDK installation and setup
- SKILL scripting capabilities for work automation and productivity enhancement
- Familiarity with the development of PCells using SKILL
- IC package design and wire bonding
- Experience with AWS System Administration
For more information and to apply, please click APPLY NOW to be contacted to discuss your expectations and particulars of this opportunity. Visa sponsorship is not possible.