I'm currently working with a global Semiconductor R+D team
headquartered in Belgium
who are looking for a Junior Analog IC Layout
engineer to join them for a long-term project
. They are currently working on a large number of projects, from Life Sciences and Wireless Communications, through to state of the art Image Sensor development. As the right candidate for the role you would be willing to commit to working on-site initially until the end of 2020 and will have 3-5 years of industry experience
as an Analog IC Layout engineer. Experience in 90nm CMOS
technology using Cadence tools and an understanding of top and block level layout would be preferred.
- 3-5 years of industry experience in Analog IC Layout
- Able to commit to a long-term project on-site
- Knowledge in technology down to 90nm in CMOS process
If this is the type of role you are looking for then hit the Apply button now. Or reach out to me via +44(0)1189 073 071 for more details either about this role, the market or contracting in general!