NOW HIRING!! ASIC Design Engineer in the Capital of France…Paris! This is a superb opportunity to join my client a leading developer and provider of 5G and 4G chips and modules for IoT devices in the lively and cultural City of Paris.
I am looking for a Senior ASIC Designer to join my client’s ASIC team in charge of the specification, design and validation of various modules linked to next generation chipsets in the IoT/5G market.
As the successful ASIC Design Engineer you will cover full-life-cycle including specification, design and validation of various modules in the PHY and MAC layers of my clients next generation chipsets and supporting the physical design team in High-Level Block closure.
More specifically responsibilities will include the Specification and microarchitecture of IC features, Implementation and maintenance of features in RTL, Support Platform Integration and SW team in their use of the designed features and Gate-Level simulations. JOB QUALIFICATIONS
Note: You must have French working rights and be able to communicate in English.
- B.Sc. / higher degree in Electrical Engineering / Computer Engineering
- At least 5 years of hands-on experience in PHY / signal processing or MAC and Network
- Excellent knowledge and experience in Micro-Architecture and implementation using Verilog/System Verilog
- Solid work experience involving Synthesis & STA – an advantage
- Experience with multi-clock domain designs – an advantage
- Familiar with all front-end tools including lint, CDC and synthesis – an advantage
For more information and a detailed discussion please contact Rachel Mason at IC Resources.