CPU Front end Design engineer - ASIC, Lyon

CPU Front end Design engineer - ASIC, Lyon

Job ID: 162335
Location: Lyon, Auvergne-Rhône-Alpes, France, Europe
Salary: Excellent salary up to €70,000 + stock options
Job Type: Permanent
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Superb Salary + Stock options + beautiful location!
Based in the beautiful City of Grenoble my client is a fabless semiconductor company with big growth plans and ambition.
I am looking for a CPU ASIC design engineer to join the team!
You will be responsible for RTL design (system Verilog), Performance assessment though SDC constraints and synthesis trials, and through simulation at CPU subsystem-level or chip-level and in collaboration with verification and software teams. You will also be required to define microarchitecture updates or new IPs to implement new features.
Required skills:
  • Familiarity with low power design techniques and methodologies.
  • Good knowledge of Verilog and/or SystemVerilog
  • Knowledge of the overall ASIC design flow
  • RTL simulation and debug using EDA tools
  • Knowledge of usual EDA scripting languages (TCL etc)
  • Command of CPU/DSP core microarchitecture principles  
Desired skills:
  • Knowledge of RISC-V
  • Knowledge of CPF and/or UPF formats
  • Knowledge of verification techniques – UVM is a plus
  • C programming in embedded environments.
You must come from a background with a master’s degree or with a specialisation in microelectronics. Have significant experience in ASIC RTL design of complex programmable cores, preferably RISC processors, if possible, for an ultra-low-power target and experience in other parts of ASIC design flow is a plus: RTL checks, verification, backend, timing analysis.
As a company you can expect an excellent salary, compensation package and stock options plan!
Apply now!!

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