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DFT Engineer - ASIC, Remote


DFT Engineer - ASIC, United Kingdom


Job ID: 175095
Location: Remote, UK
Salary: Dependent on location - shares, bonus and flexible working
Job Type: Permanent


DFT Engineer

Emerging Semiconductor company landing in the UK!!

This is a truly remarkable and exciting opportunity to join my client; a fabless semiconductor company and provider of commercial RISC-V processor IP and silicon chips!

Initially I am looking for DFT Engineers to be based in the UK.

You will be instrumental in the companies UK and European growth strategy as they look to dominate and cement their space in the European market. Headquartered in the USA and with industry leading investors there is no better time to be a part of this fantastic journey.

As the leading commercial provider of RISC-V processor IP, you will get the opportunity to work across many of the industry’s leading markets including 5G, edge AI, storage, and consumer devices whilst working on products including cores, SoCs, IPs, and development boards.

As a DFT/BIST Engineer in the Implementation team, you will contribute to the development of industry-leading CPU IP to support the company vision of enabling chip design by anyone.

Responsibilities:
  • Architect and implement MBIST solutions across our portfolio of RISC-V CPU’s
  • Evaluate and implement solutions to enable high scan test coverage for our RISC-V CPU’s
  • Support customers in all aspects of DFT: MBIST, scan and boundary scan insertion, scan compression, ATPG, and JTAG.
Requirements:
  • 5+ years of DFT experience including architecture specification, implementation, test pattern development and verification
  • Experience with MBIST insertion, simulation, and verification on RTL and Gate Level Netlist
  • Experience with Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis
  • Scan ATPG pattern generation, simulation and debug on RTL and Gate Level Netlist
  • Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys)
  • STA DFT Test mode timing constraint development and analysis
  • In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
  • TCL scripting; Python scripting is a plus

For more information contact Rachel Mason at IC Resources – 0118 9881107

 

 


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