Exciting new opportunity as Senior Design Verification Engineer to join the world leader in on-chip interconnect technology integration and deployment for SoCs.
Located in new offices in the tech hub of the Valbonne area, my client provides semiconductor intellectual property (IP) for some of the best known brands in the world - covering a wide range of applications from AI to cars, mobile phones, IoT, cameras, and SSD controllers.
As Senior Design Verification Engineer, you will be working with skilled engineers who are passionate about what they do - and want the same from you!
As part of the role, you will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between. Responsibilities:
Experience, Requirements and Qualifications:
- Advanced UVM based test bench development and debugging
- Defining, documenting, developing and executing RTL verification test/coverage at system level
- Performance verification and power-aware verification
- Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
- Help improve and refine verification process, methodology, and metrics
- UVM expertise on complex SoC projects from test bench development to verification closure
- 10 or more years of design and verification experience - interconnect verification experience is a bonus
- Strong RTL (Verilog) and UVM/C test bench debugging skills
- Experience integrating vendor provided VIPs for unit and system level verification
- Experience with Arm AMBA protocols
- This opportunity involves high performance, low power designs on a highly visible project
If you'd like to know more, please contact Rob Hudson @ IC Resources
- MS degree in EE, CS, or equivalent preferred. BS degree minimum.