This is a superb opportunity for a Design Lead to join my clients team managing around 10 people in the lively city of Paris!
As part of the role you will be expected to lead and support a Digital IC design team of 10 people from RTL to GDSII. It is imperative for this role that you can participate, in close collaboration with the Analog/Mixed-Signal architect and project technical leader, to the define ASIC architecture and verification methodology as well as the the back-end team to define the floorplan strategy to meet timing requirements
Qualification and Experience
You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in chip-level and circuit-level architecture definition, RTL design and verification
You have a solid background in digital electronic and signal processing
You have a very good vision of the entire digital ASIC design flow from RTL to GDSII
You have a strong experience in digital ASIC project and team management
You have an experience in the design of high-speed digital signal processing blocks with multi-power and multi-clock domain constraints
You have solid knowledge of a digital hardware description languages (VHDL or Verilog), System Verilog and scripting languages (TCL, Perl, Python)
Previous experience with Cadence or Synopsys RTL design flow is a plus
For more information and to discuss the role in more detail please contact Rachel Mason at IC Resources.