Job ID: 162612
Location: Marseille, Paris, Lyon, Île-de-France, Auvergne-Rhône-Alpes, France, Europe
Salary: Dependent on experience and Location
Job Type: Permanent
This is a fantastic opportunity for a Lead or principal implementation engineer to take the next step in their career and have the opportunity to lead and develop a team in a location of their choice! Paris, Sophia Antipolis or Grenoble.
My client is designing a high-performance, low-power microprocessor for a European exascale supercomputer. This new generation of microprocessors will enable them to be the leading supplier of microprocessors in Europe within high performance computing, artificial intelligence and connected mobility.Role
As part of this role you will be responsible for the whole implementation process of the first chip from gate-level to GDS, including part of the design signoff in RTL format. You will work together with 3rd party ASIC services in the first project, while building the design team according to the plan. This team will be based around you! So this is truly a fantastic opportunity to be a part of something big! Experience:
The chip integration experience must include;
- RTL design – Verilog/System Verilog
- Integration, synthesis and verification.
- Experience of signoff with at least 1 chip product being designed successfully
- Senior experience in using Synopsys implementation tools
- Experience in using Mentor and Synopsys physical verification tools
- Experience in high performance chips
APPLY NOW! Or for more information and a detailed discussion contact Rachel Mason at IC Resources.