Digital Verification Engineer, Stuttgart

Digital Verification Engineer, Stuttgart

Job ID: 161599
Location: Stuttgart, Baden-Wurttemberg, Germany, Europe
Salary: €60000 per annum
Job Type: Permanent

We support our client, a semiconductor company situated at the beautiful Lake Constance with their search for a Digital Verification Engineer.

For this technically challenging position in digital verification engineering we are looking for digital verification engineers with an experience in digital design and verification of at least 5 years. As a digital verification engineer you will require solid knowledge of HW description languages like Verilog, SystemVerilog or similar, a university degree in Electrical Engineering or Electronics or equivalent and solid debugging skills and experience with UVM or OVM. For this position you also bring good C/C++ knowledge for verification.

In the position of a digital verification engineer you will:
  • develop verification solutions for ASICs
  • carry out functional verification planning and develop test cases
  • constantly improve the script environment
  • develop prototyping solutions
  • initiate the introduction of new tools
If this vacancy sounds appealing to you, please contact Nicole Lamprecht.

+44 (0)118 988 1150

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