FPGA/ASIC Digital Designer
Poland, Europe
Permanent
Salary from €30,000- €70,000
V-165476
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Andrew Emberson
FPGA
We are searching for a number of talented FPGA/ASIC Digital Design Engineers to work on development of Machine Learning Accelerators.
Our client is expanding their Digital Design team in Poland, Warsaw and they are looking for multiple hardware engineers to join. You would get the opportunity to work in a challenging and creative environment working on architecture, design and verification using RTL. This is a great opportunity that will help you learn a lot and take on a variety of responsibilities.
The successful FPGA Design Engineer will have:
• Bachelors, Masters, PhD or equivalent qualification in Electrical Engineering, or similar (2:1 or above)
• Hands-on FPGA or ASIC development successes
• RTL Development with VHDL or Verilog
• Desired experience in hardware acceleration of mathematical algorithms.
You’ll learn lots of new skills and enjoy working in a very positive, collaborative environment, with good energy, and excellent prospects for long-term career growth.
Contact Andrew Emberson at IC Resources for more information.
Our client is expanding their Digital Design team in Poland, Warsaw and they are looking for multiple hardware engineers to join. You would get the opportunity to work in a challenging and creative environment working on architecture, design and verification using RTL. This is a great opportunity that will help you learn a lot and take on a variety of responsibilities.
The successful FPGA Design Engineer will have:
• Bachelors, Masters, PhD or equivalent qualification in Electrical Engineering, or similar (2:1 or above)
• Hands-on FPGA or ASIC development successes
• RTL Development with VHDL or Verilog
• Desired experience in hardware acceleration of mathematical algorithms.
You’ll learn lots of new skills and enjoy working in a very positive, collaborative environment, with good energy, and excellent prospects for long-term career growth.
Contact Andrew Emberson at IC Resources for more information.