We are currently working with a Bristol based client who are looking a Digital Verification engineer to joint the team at there Bristol based site. Due to Covid restrictions remote working is possible however the client would like engineers to make visits to site once restrictions are lifted.
Key Responsibilities of the Role :
- Work as part of a team and implement parts of test bench using System Verilog UVM.
- Develop System Verilog models, scoreboards, monitors.
- Efficiently debug SV model or c-model or RTL.
- Analyzing test regression fails, debugging and fixing existing code as well.
- Develop Efficient Coverage model and effectively analyse and close coverage targets.
If this position looks of interest please get in touch to discuss?