GRADUATE ASIC ENGINEER: NEW – 5G Leader, Global Semiconductor giant! 2 days in office per week, excellent benefits! This is a superb opportunity to join my client in in their cross-functional & cross-geo team to develop SoC solutions for cutting-edge products.
Educational grades for graduates: Excellent A-Levels (A’s) AND/OR a 1st/2.1/2.2 from a Digital Engineering degree
You will actively contribute in architecture design, logic design, low power design techniques and design verification strategies. Defines module interfaces/formats for simulation. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and low power implementation. Uses language such as HDL (Verilog/System Verilog), C, perl/python/tcl. Hands-on experience with Verilog/System-Verilog and scripting is required. Expertise in front-end design flow involving RTL design and integration, low power design techniques, RTL quality checks (lint, CDC etc) is highly desirable. Skills and experience we would love to see:
For more information on this role and to join a superb group which not only offers job challenge and satisfaction but also the opportunity to grow and work on technologies no other business is than contact Rachel Mason at IC Resources.
- Bachelor's or master’s degree in Electrical Engineering, Electronics Engineering or Computer Engineering.
- 1+ years digital RTL design or related work experience / Academically relevant experience.
- Hands-on experience with Verilog/System-Verilog and scripting is required
- Experience in front-end design flow involving RTL design, low power design techniques, RTL quality checks (lint, CDC etc) is highly desirable
- Good understanding of ARM processors, AHB/AXI bus, low power design techniques is desirable
- Exposure to end-to-end SoC design flows would be an added advantage