This is an exciting opportunity for a Physical Design Engineer to join my client, an innovative deep-learning vision processing start up, developing ground-breaking products for the rapidly expanding machine learning market.
Located close to London this is an attractive opportunity for an Engineer seeking to take the next step in their career and help drive and grow the Physical Design and Implementation capabilities within my clients SoC team as well as providing technical expertise and guidance regarding improvements that can be made to address SoC level Physical Design issues
I am looking for an experienced, self-driven and motivated individual who can help and contribute to the Physical Design implementation for SoCs. As an experienced PD engineer you will be involved in all aspects of physical implementation. This will include EDA flow scripting, synthesis, timing constraints generation as well as block/subsystem level Physical Design and macro IP integration. Experience and expertise in the following areas is also preferred, low power and physically aware synthesis methodologies, P&R, CTS, STA, Formal Verification, DFT.
You will come from a desired background whereby you have skills and experience in Tapeouts of complex multi-clock domain SoCs in advanced technology nodes, eg 16nm FinFET and below, low power optimization methodology and techniques, STA and timing closure, Place & Route, Integration of IP subsystems and scripting skills (TCL/Python/Perl)
In addition, good exposure and knowledge of the following would be an advantage:
- Digital ASIC front end Design and verification.
- Knowledge of Verilog HDL
- Physical Design Checks (DRC/LVS)
For more information and a confidential discussion contact Rachel Mason @ IC Resources.