I am looking for a Physical Design Engineer to be based in Cambridge and working for a leading semiconductor company.
Based in the Cambridge office the Physical design Engineer will play a key role as a contributor on the implementation of mixed signal chips with a focus on digital place and route, clock tree design along with physical and timing closure.
Key Responsibilities for this role include running place and route tools and achieving timing closure. As well as building clock trees and feeding back design changes to improve physical results, building chip level floorplans including macro placements and padrings. Minimum Qualifications:
- Knowledge of one or more of floor planning, place and route, clock tree design along or physical and timing closure.
- Practical experience of the associated EDA tools.
- Understanding of key scripting languages – particularly TCL.
This role would suit an engineer with 2-5 years’ experience, you will be required to be onsite most the time once restrictions lift.
- Experience of at least one area of implementation from floor planning, place and route, clock tree design or physical and timing closure
- Library and Macro preparations for place and route.
- Proficient in scripting languages (e.g. Python, Perl, TCL)
- Knowledge of Low Power Design methodologies – especially power gating.
- Understanding of synthesis and test tools and their impact on the flow.
For more information please contact Rachel Mason at IC Resources - 01189881107