Salary: Salary reflective of 5-10 years experience
Job Type: Permanent
This is a superb opportunity to join my client as a Senior Engineer working as part of a team that develops digital solutions for a new generation of mixed-signal motor control ASICs. In this position you will be responsible for the physical implementation of the main digital block of a mixed signal IC.
Define the physical and timing constraints.
Define test requirements and insert scan logic.
Perform synthesis and place and route.
Construct the block floorplan, insert clock trees, timing optimization and static timing analysis.
Verify the integrity of the block power grid, estimate the power consumption and IR drop.
Ensure that the final database is logically correct using formal verification.
Confirm that the database is manufacturable by performing physical verification.
Automatic test pattern generation and vector verification.
5+ year’s experience in Physical Design
Familiarity with Cadence Design Environment and Digital Tools
Experience of RTL synthesis including Scan Chain insertion and Synopsys Design Constraints (SDC) generation, TCL and/or Perl scripting
Knowledge of Synthesis, Floor -planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA), Timing Closure, Physical Verification and Formal Verification and ATPG.
For more information contact Rachel Mason at IC Resources – 0118 9881107