Physical Design & Implementation Team Lead
France, Europe
Permanent
Excellent salary available - dependent on experience level
V-171462
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Rob Hudson
ASIC | Verification
This is a superb opportunity for a Physical Design & Implementation Team Lead to be part of a company paving the way for next innovations in SoC & ASIC design. You will get the opportunity to work with teams from different technical areas in which new creative and innovative ideas will be made!!
This is a challenging position and an opportunity to work within a highly qualified team - on one of the most exciting new semiconductor products and on the most advanced process nodes (from 180nm to 5nm and beyond).
Job description
You will lead and support Digital IC Physical team from concept to GDSII. You will be responsible to drive the definition, development and verification of the IPs to bring them into production. You will continuously look for opportunities to improve methodologies and flows.
Desired skills and experience
This is a challenging position and an opportunity to work within a highly qualified team - on one of the most exciting new semiconductor products and on the most advanced process nodes (from 180nm to 5nm and beyond).
Job description
You will lead and support Digital IC Physical team from concept to GDSII. You will be responsible to drive the definition, development and verification of the IPs to bring them into production. You will continuously look for opportunities to improve methodologies and flows.
Desired skills and experience
- 10+ years of hands-on experience in IC Physical Design (and preferably implementation too)
- Experience leading a team of highly experienced physical design and implementation engineers
- End to end understanding of the digital ASIC design flow, RTL to GDSII
- In depth knowledge of digital EDA tool flows (Cadence, Synopsys, Mentor)
- Experience on advanced technology nodes, such as 28nm, 16nm, 14nm and below is required
- Experience with make files and scripting languages such as Tcl, Python and bash
- Experience at IP level and IP integration at top level are a plus
- FPGA architecture and FPGA software knowledge are a plus
- Technical background in RTL design (VHDL, Verilog, SystemVerilog) and/or RTL synthesis is a plus
- Programming experience in C/C++ or similar language is a plus
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