Fantastic new opportunity as Physical Implementation Engineer to work for a rapidly growing ASIC design and supply services company, based in the beautiful foothills of the French Alps.
You will be working with an established team of digital and analog designers on exciting mixed ASIC projects, for a variety of applications and industries. Responsibilities
As part of the ASIC/SoC design department, you will have end-to-end responsibility for the physical implementation process: synthesis, DfT, floorplan, clock tree synthesis, place & route and verifications (STA, consumption analysis, thermal analysis, proof of equivalence, DRC, LVS, IR- Drop). Required skills
- Strong knowledge of RTL - GDSII
- Understanding of DFT requirements
- Timing / STA, RTL code, basic circuit architecture
- Set up environments and synthesis / DfT / Place & Route flows to realise low voltage and low power implementations
- ISO9001 / ISO13485 / EN9100 standards
For more details or to have a chat about your situation, please contact Rob Hudson @ IC Resources
- Engineering degree (or similar) in microelectronics
- 5 years’+ experience in physical implementation (DfT or place & route + STA ) with: ability to set up a flow for a circuit of a certain complexity or in a new environment, knowledge of several technologies from 180nm down to 22FDX (and more advanced is a plus), autonomy in TCL scripts (e.g. Python), ability to write timing constraints, UPF / CPF files.
- Fluent English / Fluent French is a bonus!
- Confident skills in one of the following;
- P&R tool (ICC2 – Synopsys, Innovus-Cadence)
- static timing analysis (PrimeTime)
- logical synthesis (Design Compiler)
- DfT (Tessent)
- logic or analog or mixed simulation for electrical simulations
- IR-Drop analysis