Global Semiconductor Giant – Principal Verification Engineer
This is a huge opportunity to join a global semiconductor giant in the heart of the Thames Valley as they grow this division. You will join as the Verification expert within the team and be accountable for all Verification activities. This will give you the platform to work within an organisation who are a world-leading provider of low-power, advanced mixed-signal ICs creating the next generation of innovative, smart connected devices.
The successful Verification Engineer will have responsibilities which include; guarantee specification compliance of digital or mixed signal design by means of advanced verification methodologies and concepts. It involves definition, deployment and improvement of state-of-the-art verification methodologies. As well as Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.
You will also be tasked with the following:
- Develop efficient, reusable state-of-the-art verification environments and testbench structures.
- Develop verification strategy for digital and mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM.
- Initiate and participate in review meetings with design and verification engineers.
- Lead digital verification of mixed signal ICs or sub-systems.
- Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.
- Mentor verification team and provide technical support for verification activities
For more information and a confidential discussion please contact Rachel Mason at IC Resources – 0118 9881107
- 8-10 years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs
- System Verilog for verification using advanced verification methodologies (preferably UVM or similar such as Specman-e, OVM, SystemC, etc.)
- Assertion based verification and Formal verification.
- Expert in constrained random verification and metric driven verification.
- Expert in simulation and regressions tools e.g. Cadence Incisive, vManager, IMC
- Familiar with either Verilog or VHDL RTL coding and ASIC design methodology
- Good knowledge of UNIX shell scripting, Perl and TCL scripting