SENIOR ASIC Design Engineer: NEW – 5G Leader, Global Semiconductor giant! 2 days in office per week, excellent benefits! This is a superb opportunity to join my client in in their cross-functional & cross-geo team to develop SoC solutions for cutting-edge products.
As the successful Senior ASIC Engineer you will oversee specifications, design, RTL coding, verification, and documentation for ASIC development for a variety of products in Voice & Music and IoT sectors.
You will actively contribute in architecture design, logic design, low power design techniques and design verification strategies. Defines module interfaces/formats for simulation. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and low power implementation. Uses language such as HDL (Verilog/System Verilog), C, perl/python/tcl. Hands-on experience with Verilog/System-Verilog and scripting is required. Expertise in front-end design flow involving RTL design and integration, low power design techniques, RTL quality checks (lint, CDC etc) is highly desirable. Skills and Experiences desired:
- Good understanding and experience in ASIC development flows including logic design, RTL coding, verification, synthesis and timing closure.
- System Verilog or Verilog hardware description languages
- Familiarity in advanced low-power SoC design technique
- Experiences with ARM/DSP, AHB/AXI bus, NoC and peripheral (I2C, I2S, USB etc) development.
For more information on this role and to join a superb group which not only offers job challenge and satisfaction but also the opportunity to grow and work on technologies no other business is than contact Rachel Mason at IC Resources.
- Bachelors or master’s in electrical engineering, Computer Science or Computer Engineering.
- 4+ years ASIC design, verification, or related work experience.
- Experience going through full ASIC development cycle including concept, specification, design, verification and documentation
- Experience and knowledge of ARM processors, AHB/AXI bus, low power design techniques
- Hands-on experience with Verilog/System-Verilog and scripting is required.
- Expertise in front-end design flow involving RTL design and integration, low power design techniques, RTL quality checks (lint, CDC etc) is highly desirable.