We are recruiting for a Senior Digital Physical Design Engineer for our expanding Semiconductor client based in the French-speaking region of Switzerland.
Our client are well-known experts in low-power integrated circuit design for a whole host of application areas, ranging from automotive, consumer, communications and avionics. They have grown year on year, and now seek an experienced Digital Physical Design Engineer / Digital Backend Design Engineer to join then.
As the Digital Physical Design Engineer here you will be responsible for Static Timing Analysis, Place & Route and Physical Verification of ICs. You will take ownership for the defining the physical constraints of implemented blocks, as well as floorplanning, logic placement, Clock Tree Synthesis and timing optimisation.
- A degree (Bachelors, Masters or PhD) in microelectronics or similar
- A solid understanding of the full RTL-GDSII flow
- Several years’ experience working in Digital Physical Design / Digital Backend Design
- Expertise in:
- Static Timing Analysis (STA)
- Place & Route (P&R)
- Physical verification
You will need to speak fluent English and have a great team work ethic. Our client is a very friendly, welcoming company, which encourages ideas and innovation, and rewards achievement.
For details, contact Caroline Pye @ IC Resources, or call +44 1189881152.
Please note visa sponsorship cannot be provided for this position.