SENIOR STAFF/TECH LEAD for Physical Design – Cambridge Based in the Cambridge office, this is a great opportunity for a current Staff/Principal level engineer with some lead experience to join this global giant!
This role is for an individual who is able to act as a key technical contributor and also able to lead a technical team in the development of mixed signal, low-power chips.
As a team lead / manager you will be expected to help support your team’s professional development, set goals and manage innovation to help create the next generation of world-leading products.
As a group they cover the full RTL to GDS flow: synthesis, DFT, place and route, clock tree design, timing closure and physical signoff. Significant experience in one or more of: synthesis, timing analysis, physical implementation and digital test is required. Minimum Qualifications:
Synthesis, STA, place and route, PNR, DFT, DRC, LVS, floorplanning, PNR, clock tree, timing closure, low power, physical design, layout, CLP, CPF, UPF
- Practical experience of using / debugging industry leading EDA tools
- Proven ability to work as part of a larger team, meet project milestones and contribute to the design review processes.
- Ability to mentor and develop junior team members
- Proficient in developing timing constraints and STA signoff for advanced nodes
- Ability to write RTL (e.g. Verilog) or develop gate-level verification tests
- Knowledge of Low Power Design methodologies (e.g. CPF/UPF, power gating)
- Experience of developing high-performance teams and successfully working with teams from around the globe.
- Hands-on experience of power analysis, power optimisation or power-grid signoff.
For more information and a confidential discussion please contact Rachel Mason at IC Resources.